Design of Low Power 2-D Dct Architecture Using Reconfigurable Architecture
نویسندگان
چکیده
منابع مشابه
Design of Low Power 2-D Dct Architecture Using Reconfigurable Architecture
This Research paper includes designing a area efficient and low error Discrete Cosine Transform. This area efficient and low error DCT is obtained by using shifters and adders in place of multipliers. The main technique used here is CSD(Canonical Sign Digit) technique.CSD technique efficiently reduces redundant bits. Pipelining technique is also introduced here which reduces the processing time.
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This Research paper includes designing a area efficient and low error Discrete Cosine Transform. This area efficient and low error DCT is obtained by using shifters and adders in place of multipliers. The main technique used here is CSD (Canonical Sign Digit) technique.CSD technique efficiently reduces redundant bits. Pipelining technique is also introduced here which reduces the processing time.
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ژورنال
عنوان ژورنال: IOSR Journal of Electronics and Communication Engineering
سال: 2012
ISSN: 2278-8735,2278-2834
DOI: 10.9790/2834-0312025